Design of Energy-Efficient CMOS Circuits for AI Applications

Authors

DOI:

https://doi.org/10.62802/sx8jb163

Keywords:

CMOS Circuits, Energy Efficiency, AI Hardware, Low-Power Design, Dynamic Power Reduction, Neuromorphic Computing, Edge AI, Transistor Optimization, Clock-Gating, Sustainable Computing

Abstract

The design of energy-efficient CMOS circuits has become a critical area of research, driven by the escalating demand for artificial intelligence (AI) applications that require immense computational power. This study investigates advanced techniques for optimizing CMOS (Complementary Metal-Oxide-Semiconductor) circuit architectures to enhance energy efficiency without compromising performance. Key areas of focus include reducing dynamic and static power consumption through innovative transistor-level designs, clock-gating strategies, and the integration of advanced materials. Additionally, the research explores the potential of hybrid architectures combining CMOS with emerging technologies like memristors and neuromorphic circuits. By addressing power constraints in AI hardware, the study aims to contribute to the development of scalable, sustainable computing systems for machine learning, neural networks, and edge AI devices. The findings have broad implications for the future of AI hardware, offering solutions that balance computational demands with energy sustainability.

References

Aswathy, N., Sivamangai, N. M., Napolean, A., & Jarin, T. (2024). Design of energy-efficient hybrid STT-MTJ/CMOS-based LIM logic gates for IoT applications. Measurement: Sensors, 32, 101063.

Basha, M. M., Samalla, K., Gundala, S., Rahul, N., Sriya, D., & Deepika, S. (2024, August). Exploring energy efficient area optimized one-bit full Subtractor circuit for Signal processing application using CMOS and FinFET Technology. In 2024 2nd International Conference on Networking, Embedded and Wireless Systems (ICNEWS) (pp. 1-6). IEEE.

Hashmi, F., Nizamuddin, M., Farshori, M. A., Amin, S. U., & Khan, Z. I. (2024). Graphene nanoribbon FET technology‐based OTA for optimizing fast and energy‐efficient electronics for IoT application: Next‐generation circuit design. Micro & Nano Letters, 19(6), e70002.

Kumar, C. I., Chaudhary, A., & Upadhyaya, S. (2024). Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications. Integration, 95, 102133.

Mishty, K. F. (2024). AI-aided System and Design Technology Co-optimization Methodology Towards Designing Energy-efficient and High-performance AI Accelerators.

Nagar, P., Boruah, S., Bhoi, A. K., Patel, A., Sarda, J., & Darjij, P. (2024, January). Emerging VLSI Technologies for High performance AI and ML Applications. In 2024 International Conference on Advancements in Smart, Secure and Intelligent Computing (ASSIC) (pp. 1-5). IEEE.

Nalliboyina, K., & Ramachandran, S. (2024). An energy-efficient hybrid CMOS spiking neuron circuit design with a memristive based novel T-type artificial synapse. AEU-International Journal of Electronics and Communications, 173, 154982.

Nowshin, F., An, H., & Yi, Y. (2024). Towards Energy-Efficient Spiking Neural Networks: A Robust Hybrid CMOS-Memristive Accelerator. ACM Journal on Emerging Technologies in Computing Systems, 20(1), 1-20.

Raj, B. (2025). Energy-efficient SRAM cell design. In Sustainable Energy and Fuels (pp. 214-240). CRC Press.

Wang, K., Huang, Q., Wu, Y., Ren, Y., Wei, R., Wang, Z., ... & Huang, R. (2024). A Novel Energy-Efficient Salicide-Enhanced Tunnel Device Technology Based on 300mm Foundry Platform Towards AIoT Applications. arXiv preprint arXiv:2410.12390.

frontpage

Published

2024-11-29